Electronic devices and features comprising a layer of semiconductive material patterned with insulated features are known. Examples of such devices and circuits are disclosed in WO 02/086973 A2, WO 2006/008467 A1, and WO 2006/120414 A2. The contents of each of these documents are incorporated herein by reference. The disclosed devices include devices formed in a single layer of semiconductive material and in which a pattern of insulative features has been formed to interrupt the semiconductive layer and define at least one operational characteristic of the device. These documents also disclose certain methods suitable for forming the insulative features required to define these electronic devices in the layer of semiconductive material. Those techniques include X-ray beam and electron beam lithography. Another suitable technique disclosed is a so-called nano imprint process (from U.S. Pat. No. 5,772,905) in which a mould having extremely small projections formed by E-beam lithography is pressed into a plastics polymer layer on a substrate so as to create depressions in the layer corresponding to the mould projections. It is further disclosed that an etching process may then be carried out to expose the substrate (underlying the patterned layer) in the depression areas. In other words, the disclosed technique embosses a pattern of depressions in the upper layer supported by the substrate. The substrate is not deformed by the patterning process. The embossing process forms depressions, but generally speaking do not completely interrupt the upper layer; some of the upper layer material remains at least at the bottom of the depressions, thereby providing a connection between the upper layer material on one side of the depression with that on the other side. In order to convert an embossed depression into a fully insulating feature it is necessary to perform some post-processing, such as etching, to remove or “clean out” upper layer material from the depressions, leaving exposed insulative substrate. Clearly, whilst this imprinting or embossing technique offers some advantages in terms of facilitating the initial patterning of the upper layer, it has disadvantages as a technique for forming insulative features, because additional processing steps are required. Furthermore, this imprinting technique may undesirably distort the upper layer of semiconductive material, at least in the vicinity of each embossed trench. Furthermore, the etching technique required to expose the underlying substrate may result in undesirable removal of semiconductive material from other portions of the semiconductive layer.
It will be appreciated that in the fabrication of electronic devices and circuits, disadvantages associated with additional processing steps include the fact that the total manufacturing time is increased, and so are the complexity and costs of the overall process.
An additional problem with existing techniques for etching features in semiconductive materials is that those techniques may be suitable for use with certain materials but not others. The requirement to choose a technique compatible with the device materials being employed represents a further restriction on the process engineering.